Fault-tolerant depiction of magnetic bearing digital controller based on dual DSP
2023-06-07 13:14:43
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Fault-tolerant depiction of magnetic bearing digital controller based on dual DSP
Source: Bearing network time: 2013-09-05
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Because the magnetic suspension system is intrinsically unstable; the quality of the control system will directly determine the function of the magnetic bearing. These years, the digital control is very fast at home and abroad; the digital controller will be the main flow of the future magnetic bearing control; Digital magnetic bearing control system layout block diagram. This article from the industrial application requirements and cost thinking; the fault-tolerant depiction of the manipulator in the dotted box of Figure 1; proposed a dual DSP fault-tolerant manipulator plan; and about the sensor, coil and power Some of the amplifier's fault-tolerant depictions are not commented on in this article.
The fault-tolerant depiction of the magnetic levitation manipulator is a useful way to complete fault tolerance and improve reliability. Regarding the magnetic bearing DSP control system, its own time margin and program space margin are very limited; Hardware redundancy; that is, multi-DSP redundancy rendering is used to improve the reliability of the system.
In the multi-machine redundancy system portrayal; the key problem is the multi-machine reconfiguration strategy, the multi-machine ruling switching logic and the synchronization of multi-machine operation. The small-scale terminal system has four powerful functions related to the powerful intermediate control system. The characteristics of the system: the system layout is simple, the cost is low, the software and hardware resources are relatively lacking, it is necessary to have a good real-time function, the running time margin is too small. After the above analysis and thinking about the cost; this paper proposes to align the industry The dual-machine hot standby redundant control system is used to depict the plan.
Depicting principle The layout of the control system is shown in Figure 2. The redundant intermediate control function is completed by CPLD. The analog signal is input from the input to the two DSPs; the main DSP is selected by the intermediate ruling module; then it is disposed by the main DSP. Output to D/A converted data, timing and RS-232 output signals.
The input buffer module eliminates the influence of the input input impedance; adds a first-order buffer to the digital signal; can reduce the disturbance of the peripheral circuit. In this system, the first is to perform RS-232 and crystal, reset, external abort input signal Buffering (RS-232 output interface is controlled by the main DSP). Others; the analog signal is depicted by the voltage follower to complete the impedance matching; and the error and A/D conversion time is reduced.
The completion of the DSP clock synchronization is because the drawing plan is completely synchronized by the DSP to complete the redundant control; therefore, the dual DSP is used together to apply a crystal signal. When the system is operating; the power supply should be stabilized and the crystal oscillator should be fully oscillated; Reset the DSP. After testing the existing control system of the laboratory; the time of power supply stability and crystal oscillator stabilization is about 40ms; therefore, the reset time should be selected to be greater than this value. In addition; in order to improve its anti-interference; after reset After passing through the Schmitt trigger, the signal is best buffered by the CPLD; then it is connected to the reset end of the DSP.
The hardware fault determination module uses the output signal of each DSP CLKOUT pin as the basic condition for determining the hardware fault. If the DSP hardware works normally, the CLKOUT pin will output a fixed clock waveform. If the system CLKOUT has no clock waveform output; It will be assumed that the DSP hardware is not normal; then the intermediate ruling module is used to block the DSP. The detailed completion method is that the CLKOUT signal is sent to the monostable flip-flop 74LS123 after being completed by the CPLD; if the CLKOUT signal of the system is abnormal; 74LS123 will jump; ä¸é—´ Make the intermediate ruling module block abnormal DSP.
The output bus voting module outputs the bus voting module to complete the fault tolerance of the system; the soft fault of the disposal system. When the bus output signals of the two DSPs are compared; if it is not the same; then it indicates that some DSP or both DSPs have a soft fault; The system stops the fault output; and the intermediate ruling module handles this situation; enables the system to complete the fault-tolerant function. Consider the error of the A/D transform; this drawing only votes on the upper 8 bits of the output data bus.
The intermediate ruling module intermediate ruling module firstly analyzes the output output by the output bus voting module and the hardware fault determination module; and makes a judgment; determines that the main DSP. The main DSP function is mainly to control the external output; including the control D/A transform output And the output of RS-232.
The ruling method of the intermediate ruling module does not report an error when both the hardware decision module and the software voting module; the system selects the default DSP1 as the main DSP, and if the hardware decision module has a DSP error, it blocks the erroneous DSP; the other is the main DSP; Alarm, if both DSPs report an error; it will state the fault of the system; and provide the interface signal that the control system is faulty; let the system launch the security system in the shortest time. When neither DSP has an DSP hardware error; The software voting module reports an error; the reset signal is sent through the CPLD; the two DSPs are reset from the beginning; and the number of resets is recorded by the CPLD intermediate control module; if the system consecutive reset times exceeds four times and the correct output bus result or two DSPs are not presented online The self-test has not passed; the security system will be launched, if there is a DSP self-test does not pass; then the DSP is blocked; the system will output an alarm signal; together with the control of the main DSP to another DSP, if the reset times are less than four times; And presented the correct output bus results; CPLD module will eliminate the reset count times; the main DSP is still DSP1 .
The software flow diagram of the DSP software completion system is shown in Figure 3. The dotted line box is completed by CPLD. In the DSP system; the watchdog module is used; to deal with the system program running problem. After system reset; Detecting the watchdog circuit reset flag bit to detect the system program status; if it is the system watchdog reset; the software causes the DSP to generate an output bus error; the result is the same as the output bus error handling method, otherwise it is the reset caused by the arbitrator module; And fulfill the online self-test. If the online self-test does not pass; CPLD will actively block the hardware. The depiction is to reduce the reset time of the system and the continuity of the control system; the time of storage data is double-port RAM idt7133; this can be reset After the rapid use of the previous accounting of the temporary data (take each other's data; and the individual's data is even); so that the impact of the reset on the system is minimized.
The completion of the online self-test is controlled by the CPLD intermediate ruling module to control the signal transmission control gate; the A/D conversion is completed; the reference level is changed to 2. 5V, and then the practical control algorithm is used to calculate the result; Compare the results of CPLD with offline accounting (stored on CPLD); if the real-time accounting results are the same as offline results, it means that the system self-test passes; otherwise; actively block the DSP that does not pass the self-test.
The intermediate control module of the reliability evaluation system of the system is completed by CPLD; its reliability is much higher than that of DSP based on the program; in this system, the probability of CPLD is approximately 0; that is, the time of uniformity is far greater than that of DSP.
According to the electronic system model, the reliability of a single machine obeys the exponential distribution with time; that is, Ri(t)=e-lit (li is the disease rate); therefore, the uniformity of the single-machine system is 1/l; The time of no uniformity is:
Obviously; the no-defect moment of this system is 1.5 times of single-machine operation; the reliability of the manipulator system is greatly improved.
Conclusion The magnetic levitation fault-tolerant manipulator plan proposed in this paper; the hardware and software co-rendering is selected; the function of fault diagnosis and system reconstruction is completed; the reliability of the manipulator is greatly improved; and the function guarantee for the industrial application of magnetic bearing is provided.
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